1. Field of the Invention
The present invention is related to semiconductor memory devices, and in particular to providing a controller and an interface that can connect memory modules to a host platform. The controller and interface can advantageously conform to the PCI Express specification.
2. Description of the Related Art
Electrically erasable programmable read only memory (EEPROM) cells can store bit states, i.e. 0's and 1's, even in the event of a power outage. Hence, EEPROM cells are characterized as non-volatile memory devices. In certain configurations, the EEPROM cells in an array can be simultaneously erased, and therefore are also called “flash” memory. Compared to standard hard disks, flash memory is relatively inexpensive and requires relatively little power. Therefore, flash memory is increasingly being used to replace such hard disks in state-of-the-art devices.
An industry standard called the peripheral component interconnect (PCI) has been developed to efficiently use a bus to connect peripherals (e.g. devices including flash memory) to a host platform. Therefore, in some devices, the flash memory is controlled using an input/output (I/O) interface that uses a PCI bus. Unfortunately, this PCI bus can become the slowest link when moving data between a high-speed peripheral device, such as flash memory, and the host platform.
Specifically, the parallel buses used by PCI require a significant number of I/O signal pins. Additionally, these buses require that component, board, and system manufacturers exactly match the propagation delays of a large number of signals and clocks across a system. The degree to which this can be done directly affects the maximum clock rate that can be achieved. To accomplish this matching while maintaining backwards compatibility with regards to voltage swings can impose large power penalties.
To address these disadvantages, another industry standard called PCI Express has recently been jointly developed by Intel Corporation and the PCI Special Interest Group (PCI-SIG). PCI Express is a serial, low voltage, self-clocking I/O transfer methodology, thereby reducing the number of required pins, reducing power, and increasing bandwidth.
In light of this new transfer methodology, a need arises for a controller and an interface compatible with PCI Express that allows flash memory to be efficiently used by a host platform.